In electronic portable calculators of the type implemented in complex MOS/LSI logic permanent store memories are utilized for storing and providing large numbers of program instructions for effecting calculator operations. A calculator system implemented using only one MOS/LSI chip featuring such a permanent store memory is set forth in copending patent application, "Variable Function Calculator", Ser. No. 163,565, now abandoned and replaced by continuation application Ser. No. 420,999 and is assigned to the assignee of this invention. A calculator system implemented utilizing a plurality of MOS/LSI chips featuring a permanent store memory is set forth in U.S. Pat. No. 3,984,816, for "Expandable Function Electronic Calculator" assigned to the assignee of this invention. Conventional permanent store program memory systems utilize a large ROM in combination with an instruction register which receives the selected instruction through a parallel input. The instruction register then serializes the instruction for communication of other parts of the calculator system. Such systems, however, are not readily adapted to increasing instruction word storage capacity by addition of like memory chips. Instead, to achieve increase program memory, special purpose memory chips are required for digit coupling to the interface circuitry for the permanent store memory.
The electronic calculator system of the present invention provides a permanent store program memory having an instruction register coupled thereto for receiving in bit-parallel format a selected program instructions. The memory is addressed by an address register which also provides a code indicating whether the addressed instruction is to be subsequently decoded. The instruction register has both parallel and serial outputs and the program instruction is selectively communicated through the serial output to an output buffer. The output buffer is under control of decoding circuitry which decodes the code provided by the address register to provide a chip select signal. If a multi-chip system is utilized, each of a plurality of chips may be provided having the aforementioned program memory, instruction register and output buffer, but only one output buffer is enabled according to the code provided by each address register. The selected output buffer then provides a serial re-entry of the program instruction back into each instruction register where it is subsequently communicated through the parallel outputs to a decoder for subsequent decoding. When multi-chip systems are utilized with a plurality of chips each featuring such a multi-function memory instruction register and a output buffer, the output of all output buffers are connected in parallel so that the selected program instruction is read into all instruction registers on all chips for subsequent decoding on each chip.